1
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Consider the circuit shown in the figure. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 34 English The Boolean expression F implemented by the circuit is
A
$$\overline X \,\overline Y \,\overline Z + XY + \,\overline Y \,Z$$
B
$$\overline X \,Y\,\overline Z + XZ + \,\overline Y \,Z$$
C
$$\overline X \,Y\,\overline Z + XY + \,\overline Y \,Z$$
D
$$\overline X \,\overline Y \,\overline Z + XZ + \,\overline Y \,Z$$
2
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A programmable logic array (PLA) is shown in the figure. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 16 English The Boolean function F implemented is
A
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \overline R $$
B
$$(\overline P \, + \overline {Q\,} + \,R)(\overline P \, + Q + R) + (P + \overline P \, + \overline R )$$
C
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \,\overline R $$
D
$$(\overline P + \,\overline {Q\,} \, + R)(\overline P + Q + R) + (P + \overline {Q\,} + R)$$
3
GATE ECE 2017 Set 2
Numerical
+2
-0
Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to 0. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 15 English 1 GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 15 English 2 At t=0, the inputs to the 4-bit adder are changed to $${X_3}$$$${X_2}$$$${X_1}$$$${X_0}$$ =1100, $${Y_3}$$$${Y_2}$$$${Y_1}$$$${Y_0}$$ = 0100 and $${Z_0}$$=1. The output of the ripple carry adder will be stable at t (in ns) = ____
Your input ____
4
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
In a DRAM,
A
periodic refreshing is not required
B
information is stored in a capacitor
C
information is stored in a latch
D
both read and write operations can be performed simultaneously
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