1
GATE ECE 1997
+1
-0.3
The inverter 74AL SO4 has the following specifications:
$${I_{OH}}{\,_{\max \,}} = \, -$$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu$$A , $${I_{IL\,}}_{\max \,}$$=0.1mA. The fan out based on the above will be
A
10
B
20
C
60
D
100
2
GATE ECE 1997
+1
-0.3
For the NMOS logic gate shown in figure, the logic function implemented is
A
$$\overline {ABCDE}$$
B
$$(AB + \overline C ).(\overline {D + E} )$$
C
$$\overline {A.(B + C) + D.E}$$
D
$$(\overline {A + B} ).C + \overline D .\overline E$$
3
GATE ECE 1997
+1
-0.3
The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
A
the driver transistor has a larger threshold voltage than the load transistor.
B
the driver transistor has larger leakage currents compared to the load transistor.
C
the load transistor has a smaller W/L ratio compared to the driver transistor
D
none of the above
4
GATE ECE 1997
Subjective
+5
-0
A sequence generator is shown in figure. The counter status (Q0 Q1 Q3) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q0 till it repeats.
(b) What is the repetition rate for the generated sequence?
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