A sequence generator is shown in figure. The counter status (Q₀ Q₁ Q₃) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q₀ till it repeats.
(b) What is the repetition rate for the generated sequence?

In standard TTL the 'totem pole' stage refers to

A 2-bit binary multiplier can be implemented using

The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because