The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because

A sequence generator is shown in figure. The counter status (Q₀ Q₁ Q₃) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q₀ till it repeats.
(b) What is the repetition rate for the generated sequence?

A transmission line of 50$$\Omega $$ characteristic impedance is terminated with a 100 $$\Omega $$ resistance. The minimum impedance measured on the line is equal to

A $${\lambda \over 2}$$ section of a 600 $$\Omega $$ transmission line, short ciruited at one end and open circuited at the other end, is shown in Fig. A 100 V / 75 $$\Omega $$ generator is connected at the mid point of the section as shown in the Fig. Find the voltage at the open-ciruited end of the line.