The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because

A sequence generator is shown in figure. The counter status (Q₀ Q₁ Q₃) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q₀ till it repeats.
(b) What is the repetition rate for the generated sequence?

The inverter 74AL SO4 has the following specifications:
$${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu $$A , $${I_{IL\,}}_{\max \,}$$=0.1mA. The fan out based on the above will be

A signed integer has been stored in a byte using the 2's complement format. We wish to store the same integer in a 16-bit word. We should