The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because

For the NMOS logic gate shown in figure, the logic function implemented is

In a J_K flip-flop, we have J=$$\overline Q $$ and K=1 (see figure). Assuming the flip-flop was intially cleared and then clocked for 6 pulses, the sequence at the Q output will be

A signed integer has been stored in a byte using the 2's complement format. We wish to store the same integer in a 16-bit word. We should