In standard TTL the 'totem pole' stage refers to

The inverter 74AL SO4 has the following specifications:
$${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu $$A , $${I_{IL\,}}_{\max \,}$$=0.1mA. The fan out based on the above will be

For the NMOS logic gate shown in figure, the logic function implemented is

The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because