1
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In standard TTL the 'totem pole' stage refers to
2
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
A 2-bit binary multiplier can be implemented using
3
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
4
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
For the NMOS logic gate shown in figure, the logic function implemented is
Paper Analysis
Total Questions
Analog Circuits 7
Communications 3
Control Systems 4
Digital Circuits 9
Electromagnetics 6
Electronic Devices and VLSI 1
Engineering Mathematics 2
Microprocessors 3
Network Theory 10
Signals and Systems 7
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