1
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In standard TTL the 'totem pole' stage refers to
A
the multi-emitteer input stage
B
the phase splitter
C
the output buffer
D
open collector output stage
2
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The inverter 74AL SO4 has the following specifications:
$${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu $$A , $${I_{IL\,}}_{\max \,}$$=0.1mA. The fan out based on the above will be
A
10
B
20
C
60
D
100
3
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
For the NMOS logic gate shown in figure, the logic function implemented is GATE ECE 1997 Digital Circuits - Logic Families Question 20 English
A
$$\overline {ABCDE} $$
B
$$(AB + \overline C ).(\overline {D + E} )$$
C
$$\overline {A.(B + C) + D.E} $$
D
$$(\overline {A + B} ).C + \overline D .\overline E $$
4
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
A
the driver transistor has a larger threshold voltage than the load transistor.
B
the driver transistor has larger leakage currents compared to the load transistor.
C
the load transistor has a smaller W/L ratio compared to the driver transistor
D
none of the above
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