1
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The output of the logic gate in figure is GATE ECE 1997 Digital Circuits - Logic Gates Question 31 English
A
0
B
1
C
$$\overline A \,$$
D
A
2
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
A 2-bit binary multiplier can be implemented using
A
2 input AND gates only.
B
2 number of 2-input XOR gates and 6 number of 2-input AND gates.
C
Two 2-input NOR gates and one XNOR gate.
D
XOR gates and shift registers.
3
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In a J_K flip-flop, we have J=$$\overline Q $$ and K=1 (see figure). Assuming the flip-flop was intially cleared and then clocked for 6 pulses, the sequence at the Q output will be GATE ECE 1997 Digital Circuits - Sequential Circuits Question 61 English
A
010000
B
011001
C
010010
D
010101
4
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In standard TTL the 'totem pole' stage refers to
A
the multi-emitteer input stage
B
the phase splitter
C
the output buffer
D
open collector output stage
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