For the circuit shown in the figure, choose state variables as $${x_{1,}}{x_{2,}}{x_3}$$ to be $${i_{L1}}\left( t \right),{v_{c2}}\left( t \right),{i_{L3}}\left( t \right)$$

Wriote the state equations

$$$\left[ {\matrix{ {\mathop {{x_1}}\limits^ \bullet } \cr {\mathop {{x_2}}\limits^ \bullet } \cr {\mathop {{x_3}}\limits^ \bullet } \cr } } \right] = A\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr {{x_3}} \cr } } \right] + B\left[ {e\left( t \right)} \right]$$$

A certain linear time invariant system has the state and the output equations given below $$$\left[ {\matrix{ {\mathop {{x_1}}\limits^ \bullet } \cr {\mathop {{x_2}}\limits^ \bullet } \cr } } \right] = \left[ {\matrix{ 1 & { - 1} \cr 0 & 1 \cr } } \right]\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr } } \right] + \left[ {\matrix{ 0 \cr 1 \cr } } \right]u$$$ $$$y = \left[ {\matrix{ 1 & 1 \cr } } \right]\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr } } \right], if$$$ $${x_1}\left( 0 \right) =1 ,{x_2}\left( 0 \right) = - 1,$$ $$u\left( 0 \right) = 0,$$ then $${{dy} \over {dt}}{|_{t = 0}}$$ is

In a J_K flip-flop, we have J=$$\overline Q $$ and K=1 (see figure). Assuming the flip-flop was intially cleared and then clocked for 6 pulses, the sequence at the Q output will be

The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because