For the circuit shown in the figure, choose state variables as $${x_{1,}}{x_{2,}}{x_3}$$ to be $${i_{L1}}\left( t \right),{v_{c2}}\left( t \right),{i_{L3}}\left( t \right)$$

Wriote the state equations

$$$\left[ {\matrix{ {\mathop {{x_1}}\limits^ \bullet } \cr {\mathop {{x_2}}\limits^ \bullet } \cr {\mathop {{x_3}}\limits^ \bullet } \cr } } \right] = A\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr {{x_3}} \cr } } \right] + B\left[ {e\left( t \right)} \right]$$$

For the NMOS logic gate shown in figure, the logic function implemented is

The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because

A sequence generator is shown in figure. The counter status (Q₀ Q₁ Q₃) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q₀ till it repeats.
(b) What is the repetition rate for the generated sequence?