1
MHT CET 2025 5th May Evening Shift
MCQ (Single Correct Answer)
+1
-0

An AND gate is followed by a NOT gate in series. With two inputs ' $A$ ' and ' $B$ ', the Boolean expression for the output ' Y ' will be

A

$\overline{\mathrm{A}+\mathrm{B}}$

B

$\overline{\mathrm{A} \cdot \mathrm{B}}$

C

$\mathrm{A} \cdot \mathrm{B}$

D

$\mathrm{A}+\mathrm{B}$

2
MHT CET 2025 26th April Evening Shift
MCQ (Single Correct Answer)
+1
-0

If p-n junction diode is forward biased, then

A

electric conduction is not possible.

B

width of depletion layer decreases.

C

width of depletion layer increases.

D

barrier voltage increases.

3
MHT CET 2025 26th April Evening Shift
MCQ (Single Correct Answer)
+1
-0

In a certain 2 -inputs logic gate, when inputs $\mathrm{A}=0$ and $\mathrm{B}=0$, then output $\mathrm{C}=1$. And also when inputs $\mathrm{A}=0, \mathrm{~B}=1$, then again output $\mathrm{C}=1$. The gate must be

A

OR

B

AND

C

NAND

D

NOR

4
MHT CET 2025 26th April Evening Shift
MCQ (Single Correct Answer)
+1
-0

For a transistor, $\alpha_{\mathrm{dc}}$ and $\beta_{\mathrm{dc}}$ are the current ratios, then the value of $\frac{\beta_{\mathrm{dc}}-\alpha_{\mathrm{dc}}}{\alpha_{\mathrm{dc}} \times \beta_{\mathrm{dc}}}$

A
2.5
B
2
C
1.5
D
1

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