1
GATE EE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The saturation voltage of the ideal op-amp shown below is $$ \pm 10\,V.$$ The output voltage $${V_O}$$ of the following circuit in the steady-state is
2
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
The transfer characteristic of the Op-amp circuit shown in figure is
A
B
C
D
3
GATE EE 2014 Set 3
Numerical
+2
-0
A hysteresis type $$TTL$$ inverter is used to realize an oscillator in the circuit shown in the figure.
If the lower and upper trigger level voltages are $$0.9$$ $$V$$ and $$1.7$$ $$V,$$ the period (in $$ms$$), for which output is LOW, is ____________.
Your input ____
4
GATE EE 2014 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Given the Op-amps in the figure of ideal, the output voltage $${V_0}$$ is
Questions Asked from Operational Amplifier (Marks 2)
Number in Brackets after Paper Indicates No. of Questions
GATE EE 2025 (2)
GATE EE 2024 (1)
GATE EE 2023 (1)
GATE EE 2022 (2)
GATE EE 2017 Set 1 (1)
GATE EE 2017 Set 2 (1)
GATE EE 2015 Set 1 (1)
GATE EE 2015 Set 2 (1)
GATE EE 2014 Set 3 (2)
GATE EE 2014 Set 1 (2)
GATE EE 2013 (1)
GATE EE 2009 (2)
GATE EE 2008 (4)
GATE EE 2007 (2)
GATE EE 2006 (1)
GATE EE 2005 (2)
GATE EE 2004 (3)
GATE EE 2003 (1)
GATE EE 2002 (1)
GATE EE 2001 (2)
GATE EE 2000 (1)
GATE EE 1998 (1)
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GATE EE 1992 (2)
GATE EE 1991 (1)
GATE EE Subjects
Electromagnetic Fields
Signals and Systems
Engineering Mathematics
General Aptitude
Power Electronics
Power System Analysis
Analog Electronics
Control Systems
Digital Electronics
Electrical Machines
Electric Circuits