The op-amp shown in the figure has a finite gain $$A = 1000$$ and an infinite input resistance. A step voltage $${V_i} = 1\,\,mV$$ is applied at the input at time $$t = 0$$ as shown. Assuming that the operational amplifier is not saturated, the time constant (in millisecond) of the output voltage $${V_o}$$ is

The saturation voltage of the ideal op-amp shown below is $$ \pm 10\,V.$$ The output voltage $${V_O}$$ of the following circuit in the steady-state is

A hysteresis type $$TTL$$ inverter is used to realize an oscillator in the circuit shown in the figure.

If the lower and upper trigger level voltages are $$0.9$$ $$V$$ and $$1.7$$ $$V,$$ the period (in $$ms$$), for which output is LOW, is ____________.

The transfer characteristic of the Op-amp circuit shown in figure is