An output device is interfaced with $$8$$ bit microprocessor $$8085$$$$A.$$ The interfacing circuit is shown in figure

The interfacing circuit makes use of $$3$$ line to $$8$$ line decoder having $$3$$ enable lines $${E_1}\,\,\overline E {}_2,$$ $$\,\overline E {}_3$$. The address of the device is

A portion of the main program to call a subroutine $$SUB$$ in an $$8085$$ environment is given below:
$$\eqalign{ & LXI\,\,\,\,\,\,\,\,\,\,\,\,\,D\,\,\,DISP \cr & LP\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,CALL\,\,\,SUB \cr} $$

It is desired that control be returned to $$LP+DISP+3$$ when the $$RET$$ instruction is executed in the subroutine. The set of instructions that precede the $$RET$$ instruction in the subroutine are

When a $$''CALL$$ $$addr'$$ instruction is executed, the $$CPU$$ carries out the following sequential operations internally.

Note:
$$(R)$$ means content of register $$R$$
$$\left( {\left( R \right)} \right)$$ means content of memory locating pointed by $$R$$
$$PC$$ means Program Counter
$$SP$$ means Stack Pointer

In $$8085$$ microprocessor, the contents of the Accumulator, after the following instructions are executed will become

$$\eqalign{ & XRA\,\,\,A \cr & MVI\,\,\,B\,\,\,F0\,\,\,H \cr & SUB\,\,\,B \cr} $$