1
GATE EE 2014 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Which of the following logic circuits is a realization of the function $$F$$ whose karnaugh map is shown in figure GATE EE 2014 Set 1 Digital Electronics - Minimization Question 3 English
A
GATE EE 2014 Set 1 Digital Electronics - Minimization Question 3 English Option 1
B
GATE EE 2014 Set 1 Digital Electronics - Minimization Question 3 English Option 2
C
GATE EE 2014 Set 1 Digital Electronics - Minimization Question 3 English Option 3
D
GATE EE 2014 Set 1 Digital Electronics - Minimization Question 3 English Option 4
2
GATE EE 2010
MCQ (Single Correct Answer)
+2
-0.6
A minimized form of the function $$F$$ is GATE EE 2010 Digital Electronics - Minimization Question 5 English
A
$$F = \overline X \overline Y + YZ$$
B
$$F = \overline {XY} + YZ$$
C
$$F = \overline {XY} + Y\overline Z $$
D
$$F = \overline {XY} + \overline Y Z$$
3
GATE EE 2010
MCQ (Single Correct Answer)
+2
-0.6
Which of the following circuits is a realization of the previous function $$F$$ $$?$$
A
GATE EE 2010 Digital Electronics - Minimization Question 4 English Option 1
B
GATE EE 2010 Digital Electronics - Minimization Question 4 English Option 2
C
GATE EE 2010 Digital Electronics - Minimization Question 4 English Option 3
D
GATE EE 2010 Digital Electronics - Minimization Question 4 English Option 4
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