1
GATE EE 2010
MCQ (Single Correct Answer)
+2
-0.6
The $$TTL$$ circuit shown in the figure is fed with the waveform $$X$$ (also shown). All gates have equal propagation delay of $$10$$ $$ns.$$ The output $$Y$$ of the circuit is GATE EE 2010 Digital Electronics - Logic Families and Memories Question 2 English 1 GATE EE 2010 Digital Electronics - Logic Families and Memories Question 2 English 2
A
GATE EE 2010 Digital Electronics - Logic Families and Memories Question 2 English Option 1
B
GATE EE 2010 Digital Electronics - Logic Families and Memories Question 2 English Option 2
C
GATE EE 2010 Digital Electronics - Logic Families and Memories Question 2 English Option 3
D
GATE EE 2010 Digital Electronics - Logic Families and Memories Question 2 English Option 4
2
GATE EE 2006
MCQ (Single Correct Answer)
+2
-0.6
A TTL NOT gate circuit is shown in figure. Assuming $${V_{BE}} = 0.7\,v$$ of both the transistors, if $${V_i} = 3.0\,V,$$ then the states of the two transistors will be GATE EE 2006 Digital Electronics - Logic Families and Memories Question 1 English
A
$${Q_1}\,\,ON$$ and $${Q_2}\,\,OFF$$
B
$${Q_1}$$ reverse $$\,\,ON$$ and $${Q_2}\,\,OFF$$
C
$${Q_1}$$ reverse $$\,\,ON$$ and $${Q_2}\,\,ON$$
D
$${Q_1}\,\,OFF$$ and $${Q_2}$$ reverse $$\,\,ON$$
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