1
GATE EE 2011
MCQ (Single Correct Answer)
+1
-0.3
The output $$Y$$ of the logic circuit given below is
2
GATE EE 2003
MCQ (Single Correct Answer)
+1
-0.3
Figure shows a $$4$$ to $$1$$ $$MUX$$ to be used to implement the sum $$S$$ of a $$1$$-bit full adder with input bits $$P$$ and $$Q$$ and the carry input $${C_{in}}.$$ Which of the following combinations of inputs to $${{\rm I}_0},\,\,{{\rm I}_1},\,\,{{\rm I}_2}$$ and $$\,\,{{\rm I}_3}$$ of the $$MUX$$ will realize the sum $$S$$?
3
GATE EE 2001
MCQ (Single Correct Answer)
+1
-0.3
The output $$f$$ of the $$4$$- to- $$1$$ $$MUX$$ shown in fig. is
Questions Asked from Combinational Circuits (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE EE Subjects
Electric Circuits
Electromagnetic Fields
Signals and Systems
Electrical Machines
Engineering Mathematics
General Aptitude
Power System Analysis
Electrical and Electronics Measurement
Analog Electronics
Control Systems
Power Electronics