1
GATE EE 2011
+1
-0.3
The output $$Y$$ of the logic circuit given below is
A
$$1$$
B
$$0$$
C
$$X$$
D
$$\overline X$$
2
GATE EE 2003
+1
-0.3
Figure shows a $$4$$ to $$1$$ $$MUX$$ to be used to implement the sum $$S$$ of a $$1$$-bit full adder with input bits $$P$$ and $$Q$$ and the carry input $${C_{in}}.$$ Which of the following combinations of inputs to $${{\rm I}_0},\,\,{{\rm I}_1},\,\,{{\rm I}_2}$$ and $$\,\,{{\rm I}_3}$$ of the $$MUX$$ will realize the sum $$S$$?
A
$${{\rm I}_0} = {{\rm I}_1} = {C_{in}};\,{{\rm I}_2} = {{\rm I}_3} = {\overline C _{in}}$$
B
$${{\rm I}_0} = {{\rm I}_1} = {\overline C _{in}};\,{{\rm I}_2} = {{\rm I}_3} = {C_{in}}$$
C
$${{\rm I}_0} = {{\rm I}_3} = {\overline C _{in}};\,{{\rm I}_1} = {{\rm I}_2} = {\overline C _{in}}$$
D
$${{\rm I}_0} = {{\rm I}_3} = {\overline C _{in}};\,{{\rm I}_1} = {{\rm I}_2} = {C_{in}}$$
3
GATE EE 2001
+1
-0.3
The output $$f$$ of the $$4$$- to- $$1$$ $$MUX$$ shown in fig. is
A
$$\overline {xy} + x$$
B
$$x+y$$
C
$$\overline x + \overline y$$
D
$$xy + \overline x$$
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