1
GATE EE 2022
Numerical
+1
-0.33

The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is ________. (round off to one decimal place).

Your input ____
2
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state. GATE EE 2014 Set 3 Digital Electronics - Sequential Circuits Question 20 English

The logic gate represented by the state diagram is

A
$$XOR$$
B
$$OR$$
C
$$AND$$
D
$$NAND$$
3
GATE EE 2014 Set 1
MCQ (Single Correct Answer)
+1
-0.3
A cascade of three identical modulo -$$5$$ counters has an over all modulus of
A
$$5$$
B
$$25$$
C
$$125$$
D
$$625$$
4
GATE EE 2012
MCQ (Single Correct Answer)
+1
-0.3
Consider the given circuit. In this circuit, the race around GATE EE 2012 Digital Electronics - Sequential Circuits Question 22 English
A
does not occur
B
occurs when $$CLK=0$$
C
occurs when $$CLK=1$$ and $$A=B=1$$
D
occurs when $$CLK=1$$ and $$A=B=0$$
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