A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state.

The logic gate represented by the state diagram is

Consider the given circuit. In this circuit, the race around

The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal available at $$Q$$ is

For a $$J$$-$$K$$ flip-flop its $$J$$ input is tied to its own $$Q$$ output and its $$K$$ input is connected to its own $$Q$$ output. If the flip-flop is fed with a clock of frequency $$1$$ $$MHz,$$ its $$Q$$ output frequency will be ______________