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1
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state. GATE EE 2014 Set 3 Digital Electronics - Sequential Circuits Question 23 English

The logic gate represented by the state diagram is

A
$$XOR$$
B
$$OR$$
C
$$AND$$
D
$$NAND$$
2
GATE EE 2014 Set 1
MCQ (Single Correct Answer)
+1
-0.3
A cascade of three identical modulo -$$5$$ counters has an over all modulus of
A
$$5$$
B
$$25$$
C
$$125$$
D
$$625$$
3
GATE EE 2012
MCQ (Single Correct Answer)
+1
-0.3
Consider the given circuit. In this circuit, the race around GATE EE 2012 Digital Electronics - Sequential Circuits Question 25 English
A
does not occur
B
occurs when $$CLK=0$$
C
occurs when $$CLK=1$$ and $$A=B=1$$
D
occurs when $$CLK=1$$ and $$A=B=0$$
4
GATE EE 2002
MCQ (Single Correct Answer)
+1
-0.3
The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal available at $$Q$$ is GATE EE 2002 Digital Electronics - Sequential Circuits Question 26 English
A
$$10$$ $$kHz$$
B
$$2.5$$ $$kHz$$
C
$$20$$ $$kHz$$
D
$$5$$ $$kHz$$
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