1
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state.
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The logic gate represented by the state diagram is
2
GATE EE 2014 Set 1
MCQ (Single Correct Answer)
+1
-0.3
A cascade of three identical modulo -$$5$$ counters has an over all modulus of
3
GATE EE 2012
MCQ (Single Correct Answer)
+1
-0.3
Consider the given circuit. In this circuit, the race around
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4
GATE EE 2002
MCQ (Single Correct Answer)
+1
-0.3
The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal available at $$Q$$ is
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Questions Asked from Sequential Circuits (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE EE Subjects
Electromagnetic Fields
Signals and Systems
Engineering Mathematics
General Aptitude
Power Electronics
Power System Analysis
Analog Electronics
Control Systems
Digital Electronics
Electrical Machines
Electric Circuits