A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state.

The logic gate represented by the state diagram is

A cascade of three identical modulo -$$5$$ counters has an over all modulus of

Consider the given circuit. In this circuit, the race around

The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal available at $$Q$$ is