GATE EE 2005 | Logic Families and Memories Question 3 | Digital Electronics

GATE EE 2005

MCQ (Single Correct Answer)

-0.3

If $${X_1}$$ and $${X_2}$$ are the inputs to the circuit shown in the figure, the output $$Q$$ is GATE EE 2005 Digital Electronics - Logic Families and Memories Question 3 English

GATE EE 2005 Digital Electronics - Logic Families and Memories Question 3 English

$$\overline {{X_1} + {X_2}} $$

$$\overline {{X_1} \bullet {X_2}} $$

$$\overline {{X_1}} \bullet {X_2}$$

$${X_1} \bullet \overline {{X_2}} $$

GATE EE 1998

MCQ (Single Correct Answer)

-0.3

In standard $$TTL$$ gates, the totem pole output stage is primarily used to

Increase the noise margin of the gate

Decrease the output switching delay

Facilitate a wired OR logic connection

Increase the output impedance of the circuit

GATE EE 1998

MCQ (Single Correct Answer)

-0.3

The open collector outputs of two$$2$$-inputs $$NAND$$ gates are connected to a common pull up resistor. If the input to the gates are $$P,Q$$ and $$R,S$$ respectively, the output is equal to

$$\overline {PQ} \,.\,\overline {RS} $$

$$\overline {PQ} \,+\,\overline {RS} $$

$$PQ+RS$$

$$PQRS$$

GATE EE Subjects

Electric Circuits

Three Phase Circuits Transient Response Graph Theory Two Port Networks Sinusoidal Steady State Analysis Network Elements Network Theorems

Electromagnetic Fields

Time Varying Fields Electrostatics Magnetostatics

Signals and Systems

Linear Time Invariant Systems Continuous and Discrete Time Signals Continuous Time Signal Fourier Transform Continuous Time Periodic Signal Fourier Series Discrete Time Signal Z Transformation Miscellaneous Continuous Time Signal Laplace Transform Sampling Theorem

Electrical Machines