A processor has $$16$$ integer registers $$\left( {R0,\,\,R1,\,\,..\,\,,\,\,R15} \right)$$) and $$64$$ floating point registers $$(F0, F1,… , F63).$$ It uses a $$2$$-byte instruction format. There are four categories of instructions: Type-$$1,$$ Type-$$2,$$ Type-3, and Type-$$4.$$ Type-$$1$$ category consists of four instructions, each with $$3$$ integer register operands $$(3Rs)$$. Type-$$2$$ category consists of eight instructions, each with $$2$$ floating point register operands $$(2Fs).$$ Type-$$3$$ category consists of fourteen instructions, each with one integer register operand and one floating point register operand $$(1R+1F).$$ Type-$$4$$ category consists of $$N$$ instructions, each with a floating point register operand $$(1F).$$

The maximum value of $$N$$ is __________.

Consider a processor with $$64$$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has $$100$$ instructions, the amount of memory (in bytes) consumed by the program text is _____________.

Consider the following code sequence having five instructions $${I_1}$$ to $${I_5}$$. Each of these instructions has the following format.

$$\,\,\,\,\,\,\,\,\,\,\,\,\,\,OP\,\,Ri,\,\,Rj,\,\,Rk$$

where operation $$OP$$ is performed on contents of registers $$Rj$$ and $$Rk$$ and the result is stored in register $$Ri.$$

$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_1}:ADD\,\,\,R1,\,R2,\,R3 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_2}:MUL\,\,R7,\,R1,\,R3 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_3}:SUB\,\,\,\,R4,\,R1,\,R5 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_4}:ADD\,\,\,R3,\,R2,\,R4 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_5}:MUL\,\,\,R7,\,R8,\,R9 \cr} $$

Consider the following three statements.

$$\,\,\,\,\,\,S1:\,\,$$ There is an anti-dependence between instructions $${L_2}$$ and $${L_5}$$
$$\,\,\,\,\,\,S2:\,\,$$ There is an anti-dependence between instructions $${L_2}$$ and $${L_4}$$
$$\,\,\,\,\,\,S3:\,\,$$ Within an instruction pipeline an anti-dependence always creates one or more stalls

Which one of above statements is/are correct?

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter $$(PC)$$ and Program Status Word $$(PSW),$$ are of size $$2$$ bytes. A stack in the main memory is implemented from memory location $${\left( {0100} \right)_{16}}$$ and it grows upward. The stack pointer $$(SP)$$ points to the top element of the stack. The current value of $$SP$$ is $${\left( {016E} \right)_{16}}$$. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word $$= 2$$ bytes). The CALL instruction is implemented as follows:

$$ \bullet \,\,\,\,\,\,\,\,$$ Store the current value of $$PC$$ in the stack
$$ \bullet \,\,\,\,\,\,\,\,$$ Store the value of $$PSW$$ register in the stack
$$ \bullet \,\,\,\,\,\,\,\,$$ Load the starting address of the subroutine in $$PC$$

The content of $$PC$$ just before the fetch of a CALL instruction is $$\left( {5FA0} \right){\,_{16}}.$$ After execution of the CALL instruction, the value of the stack pointer is