1
GATE CSE 2006
+2
-0.6
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location $$3000$$ is $$10$$ and the content of the register $$R3$$ is $$2000$$. The content of each of the memory locations from $$2000$$ to $$2010$$ is $$100.$$ The program is loaded from the memory location $$1000.$$ All the numbers are in decimal.

Assume that the memory is byte addressable and the word size is $$32$$ bits. If an interrupt occurs during the execution of the instruction $$''INC$$ $$R3'',$$ what return address will be pushed on to the stack?

A
$$1005$$
B
$$1020$$
C
$$1024$$
D
$$1040$$
2
GATE CSE 2006
+2
-0.6
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location $$3000$$ is $$10$$ and the content of the register $$R3$$ is $$2000$$. The content of each of the memory locations from $$2000$$ to $$2010$$ is $$100.$$ The program is loaded from the memory location $$1000.$$ All the numbers are in decimal.

Assume that the memory is word addressable. After the execution of this program, the content of memory location $$2010$$ is

A
$$100$$
B
$$101$$
C
$$102$$
D
$$110$$
3
GATE CSE 2005
+2
-0.6
Consider a three word machine instruction $$ADD$$ $$A$$ $$\left[ {{R_0}} \right],\,@\,B$$

The first operand (destination) ''$$A$$ $$\left[ {{R_0}} \right]''$$ uses indexed addressing mode with $${{R_0}}$$ as the index register. The second operand (source) $$''@B''$$ used indirect addressing mode. $$A$$ and $$B$$ are memory addresses residing at the second and the third words, respectively. The first word of the instruction specific the opcode, the index register designation and the source and destination addressing modes. During execution of $$ADD$$ instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

A
$$3$$
B
$$4$$
C
$$5$$
D
$$6$$
4
GATE CSE 2004
+2
-0.6
Consider the following program segment for a hypothetical $$CPU$$ having three user registers $$R1,R2,$$ and $$R3.$$ Consider that the memory is byte addressable with word size $$32$$ bits, and the program has been loaded starting from memory location $$1000$$ (decimal). If an interrupt occurs while the $$CPU$$ has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

A
$$1007$$
B
$$1020$$
C
$$1024$$
D
$$1028$$
GATE CSE Subjects
Discrete Mathematics
Programming Languages
Theory of Computation
Operating Systems
Digital Logic
Computer Organization
Database Management System
Data Structures
Computer Networks
Algorithms
Compiler Design
Software Engineering
Web Technologies
General Aptitude
EXAM MAP
Joint Entrance Examination