A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

R-type Instruction Format:

OPCODE | UNUSED | DST Register | SRC Register1 | SRC Register2 |
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I-type Instruction Format:

OPCODE | DST Register | SRC Register | # Immediate value/address |
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In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let *X* be the number of bits used to encode the UNUSED field, *Y* be the number of bits used to encode the OPCODE field, and *Z* be the number of bits used to encode the immediate value/address field. The value of *X + 2Y + Z* is __________.

The maximum value of $$N$$ is __________.