1
GATE ECE 2015 Set 2
Numerical
+2
-0
The transfer function of a mass-spring damper system is given by $${\rm{G(s) = }}{1 \over {M{s^2} + Bs + K}}$$ The frequency response data for the system are given in the following table. GATE ECE 2015 Set 2 Control Systems - Frequency Response Analysis Question 18 English The unit step response of the system approaches a steady state value of ______.
Your input ____
2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A function of Boolean variables X,Y and Z is expressed in terms of the min-terms as F(X, Y, Z)=$$\sum\limits_{}^{} {} $$m(1,2,5,6,7) Which one of the product of sums given below is equal to the funtion F(X, Y, Z)?
A
$$(\overline X + \overline Y + \overline Z ).(\overline X + Y + Z).(X + \overline Y + \overline Z )$$
B
$$(X + Y + Z).(X + \overline Y + \overline Z ).(\overline X + Y + Z)$$
C
$$(\overline X + \overline Y + Z).(\overline X + Y + \overline Z ).(X + \overline Y + Z).(X + Y + \overline Z ).(X + Y + Z)$$
D
$$(X + Y + \overline Z ).(\overline X + Y + Z).(\overline X + Y + \overline Z ).((\overline X + \overline Y + Z).(\overline X + \overline Y + \overline Z )$$
3
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
In the figure shown, the output ܻ is required to be ܻ Y=AB+ $$\overline C $$$$\overline D $$. The gates G1 and G2 must be, respectively, GATE ECE 2015 Set 2 Digital Circuits - Logic Gates Question 17 English
A
NOR, OR
B
OR, NAND
C
NAND, OR
D
AND, NAND
4
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A 1-to-8 demultiplexer with data input D$$_{in}$$ , address inputs S$$_{0}$$, S$$_{1}$$, S$$_{2}$$ (with S$$_{0}$$ as the LSB) and $${\overline Y _0}$$ to $${\overline Y _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline E $$ and address inputs A$$_{0}$$ and A$$_{1}$$) as shown in the figure. $${D_{in}}$$, S$$_{0}$$, S$$_{1}$$and S$$_{2}$$ are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be GATE ECE 2015 Set 2 Digital Circuits - Combinational Circuits Question 23 English
A
$${S_2},\,{D_{in}},\,{S_0},\,{S_1}$$
B
$${S_1},\,{D_{in}},\,{S_0},\,{S_2}$$
C
$${D_{in}},\,{S_0},\,\,{S_1}\,{S_2}$$
D
$${D_{in}},\,{S_2},\,{S_0},\,{S_1}$$
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