1
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
In the figure shown, the output ܻ is required to be ܻ Y=AB+ $$\overline C $$$$\overline D $$. The gates G1 and G2 must be, respectively, GATE ECE 2015 Set 2 Digital Circuits - Logic Gates Question 17 English
A
NOR, OR
B
OR, NAND
C
NAND, OR
D
AND, NAND
2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A 1-to-8 demultiplexer with data input D$$_{in}$$ , address inputs S$$_{0}$$, S$$_{1}$$, S$$_{2}$$ (with S$$_{0}$$ as the LSB) and $${\overline Y _0}$$ to $${\overline Y _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline E $$ and address inputs A$$_{0}$$ and A$$_{1}$$) as shown in the figure. $${D_{in}}$$, S$$_{0}$$, S$$_{1}$$and S$$_{2}$$ are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be GATE ECE 2015 Set 2 Digital Circuits - Combinational Circuits Question 23 English
A
$${S_2},\,{D_{in}},\,{S_0},\,{S_1}$$
B
$${S_1},\,{D_{in}},\,{S_0},\,{S_2}$$
C
$${D_{in}},\,{S_0},\,\,{S_1}\,{S_2}$$
D
$${D_{in}},\,{S_2},\,{S_0},\,{S_1}$$
3
GATE ECE 2015 Set 2
Numerical
+1
-0
A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______. GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 50 English
Your input ____
4
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 28 English
A
mod - 2 counter
B
mod - 4 counter
C
mod - 5 counter
D
mod - 6 counter
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