A 1-to-8 demultiplexer with data input D$$_{in}$$ , address inputs S$$_{0}$$, S$$_{1}$$, S$$_{2}$$ (with S$$_{0}$$ as the LSB) and $${\overline Y _0}$$ to $${\overline Y _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline E $$ and address inputs A$$_{0}$$ and A$$_{1}$$) as shown in the figure. $${D_{in}}$$, S$$_{0}$$, S$$_{1}$$and S$$_{2}$$ are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______.

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

An air-filled rectangular waveguide of internal dimension $$a\,\,cm\,\, \times \,\,b\,\,cm$$ (a > b) has a cutoff frequency of 6 GHz for the dominant $$T{E_{10}}$$ mode. For the same waveguide, if the cutoff frequency of the $$T{E_{11}}$$ mode is 15 GHz, the cutoff frequency of the $$T{E_{01}}$$ mode in GHz is _____________