1
GATE ECE 1998
MCQ (Single Correct Answer)
+1
-0.3
An I/O processor control the flow of information between
A
cache memory and I/O devices
B
main memory and I/O devices
C
two I/O devices
D
cache and main memories
2
GATE ECE 1998
Subjective
+5
-0
Determine the frequency of resonance and the resonant impedance of the parallel circuit shown in figure. What happens when $$L = C{R^2}$$? GATE ECE 1998 Network Theory - Sinusoidal Steady State Response Question 21 English
3
GATE ECE 1998
MCQ (Single Correct Answer)
+1
-0.3
The parallel $$RLC$$ circuit shown in figure is in resonance. In this circuit GATE ECE 1998 Network Theory - Sinusoidal Steady State Response Question 48 English
A
$$\left| {{{\rm I}_R}} \right| < 1m{\rm A}$$
B
$$\left| {{{\rm I}_R} + {{\rm I}_L}} \right| > 1m{\rm A}$$
C
$$\left| {{{\rm I}_R} + {{\rm I}_C}} \right| < 1m{\rm A}$$
D
$$\left| {{{\rm I}_L} + {{\rm I}_C}} \right| > 1m{\rm A}$$
4
GATE ECE 1998
Subjective
+5
-0

A voltage source of internal impedance $${\mathrm R}_\mathrm s\;+\;{\mathrm{jX}}_\mathrm s$$ supplies power to a load of impedance $${\mathrm R}_\mathrm L\;+\;{\mathrm{jX}}_\mathrm L$$ in which only $${\mathrm R}_\mathrm L$$ is variable. Determine the value of $${\mathrm R}_\mathrm L$$ for maximum power transfer from the source to the load. Also, find the numerical value of $${\mathrm R}_\mathrm L$$ if the source impedance is 3.0 Ω (purely resistive) and $${\mathrm X}_\mathrm L$$ is 4.0 Ω.