1
MCQ (Single Correct Answer)

AIPMT 2011 Prelims

Symbolic representation of four logic gates are shown as



Pick out which ones are for AND, NAND and NOT gates, respectively
A
(ii), (iii) and (iv)
B
(iii), (ii) and (i)
C
(iii), (ii) and (iv)
D
(ii), (iv) and (iii)

Explanation

AND, NAND and NOT gates are (ii), (iv) and (iii) respectively.
2
MCQ (Single Correct Answer)

AIPMT 2011 Prelims

A transistor is operated in common emitter configuration at VC = 2 V such that a change in the base current from 100 $$\mu $$A to 300 $$\mu $$A produces a change in the collector current from 10 mA to 20 mA. The current gain is
A
50
B
75
C
100
D
25

Explanation

Current gain, $$\beta $$ = $${{\Delta {I_C}} \over {\Delta {I_B}}}$$

= $${{\left( {20 - 10} \right) \times {{10}^{ - 3}}} \over {\left( {300 - 100} \right) \times {{10}^{ - 6}}}}$$ = 50
3
MCQ (Single Correct Answer)

AIPMT 2011 Prelims

In forward biasing of the p-n junction
A
the positive terminal of the battery is connected to p-side and the depletion region becomes thick.
B
the positive terminal of the battery is connected to n-side and the depletion region becomes thin.
C
the positive terminal of the battery is connected to n-side and the depletion region becomes thick.
D
the positive terminal of the battery is connected to p-side and the depletion region becomes thin.

Explanation

In forward biasing, the positive terminal of the battery is connected to p-side and the negative terminal to n-side of p-n junction. The forward bias voltage opposes the potential barrier. Due to it, the depletion region becomes thin.
4
MCQ (Single Correct Answer)

AIPMT 2010 Mains

The following figure shows a logic gate circuit with two inputs A and B and the output Y. The voltage waveforms of A, B and Y are as given.



The logic gate is
A
NOR gate
B
OR gate
C
AND gate
D
NAND gate

Explanation

It is clear from given logic circuit, that out put Y is low when both the inputs are high, otherwise it is high. Thus logic circuit is NAND gate.

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