1
MCQ (Single Correct Answer)

AIPMT 2011 Prelims

In forward biasing of the p-n junction
A
the positive terminal of the battery is connected to p-side and the depletion region becomes thick.
B
the positive terminal of the battery is connected to n-side and the depletion region becomes thin.
C
the positive terminal of the battery is connected to n-side and the depletion region becomes thick.
D
the positive terminal of the battery is connected to p-side and the depletion region becomes thin.

Explanation

In forward biasing, the positive terminal of the battery is connected to p-side and the negative terminal to n-side of p-n junction. The forward bias voltage opposes the potential barrier. Due to it, the depletion region becomes thin.
2
MCQ (Single Correct Answer)

AIPMT 2011 Mains

A Zener diode, having breakdown voltage equal to 15 V, is used in a voltage regulator circuit shown in figure. The current through the diode is

A
5 mA
B
10 mA
C
15 mA
D
20 mA

Explanation

Voltage across 250 Ω resistance = 20 V – 15 V = 5 V

Now current through 250 $$\Omega $$ resistance: 5/250 = 20 mA

If voltage across load resistance 1 k$$\Omega $$ is 15 V, then

current through 1 kΩ is 15/1000 = 15 mA

The current through the zener diode is

= Current through 250 $$\Omega $$ resistance – Current through 1 k$$\Omega $$ resistance.

= 20 - 15

= 5 mA
3
MCQ (Single Correct Answer)

AIPMT 2011 Prelims

If a small amount of antimony is added to germanium crystal
A
it becomes a p-type semiconductor
B
the antimony becomes an acceptor atom
C
there will be more free electrons than holes in the semiconductor
D
its resistance is increased

Explanation

If a small amount of antimony is added to germanium crystal, crystal becomes n-type semiconductor. Hence, there will be more free electrons than holes.
4
MCQ (Single Correct Answer)

AIPMT 2011 Prelims

Symbolic representation of four logic gates are shown as



Pick out which ones are for AND, NAND and NOT gates, respectively
A
(ii), (iii) and (iv)
B
(iii), (ii) and (i)
C
(iii), (ii) and (iv)
D
(ii), (iv) and (iii)

Explanation

AND, NAND and NOT gates are (ii), (iv) and (iii) respectively.

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