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1

### AIPMT 2015 Cancelled Paper

If in a p-n junction, a square input signal of 10 V is applied, as shown, then the output across RL will be
A B C D ## Explanation

Here P-N junction diode rectifies half of the ac wave i.e., acts as half wave rectifier.
During + ve half cycle Diode is forward biased output across RL will be During –ve half cycle Diode is reverse biased output will not obtained.
2

### AIPMT 2015 Cancelled Paper

Which logic gate is represented by the following combination of logic gates ? A
AND
B
NOR
C
OR
D
NAND

## Explanation

The Boolean expression of this arrangement is

Y = $$\overline {\overline A + \overline B }$$ = $$\overline{\overline A} + \overline{\overline B}$$ = A.B

Thus, the combination represents AND gate.
3

### AIPMT 2015

In the given figure, a diode D is connected to an external resistance R = 100 $$\Omega$$ and an e.m.f. of 3.5 V. If the barrier potential developed across the diode is 0.5 V, the current in the citcuit will be A
20 mA
B
35 mA
C
30 mA
D
40 mA

## Explanation

Potential difference across resistance R

= 3.5 – 0.5 = 3.0 V

Current in circuit, I = V/R = 3/100 = 30 mA
4

### AIPMT 2015

The input signal given to a CE amplifier having a voltage gain of 150 is Vi = 2cos(15t + $${\pi \over 3}$$). The corresponding output signal will be
A
2cos$$\left( {15t + {{5\pi } \over 6}} \right)$$
B
300cos$$\left( {15t + {{4\pi } \over 3}} \right)$$
C
300cos$$\left( {15t + {{\pi } \over 3}} \right)$$
D
75cos$$\left( {15t + {{2\pi } \over 3}} \right)$$

## Explanation

Given, Vi = 2cos(15t + $${\pi \over 3}$$)

and Voltage gain AV = 150

For CE transistor phase difference between input and output signal is $$\pi$$ = 180o

Using formula, AV = $${{{V_0}} \over {{V_i}}}$$

$$\Rightarrow$$ V0 = AV $$\times$$ Vi

= 150$$\times$$2cos(15t + $${\pi \over 3}$$ + $$\pi$$)

= 300cos$$\left( {15t + {{4\pi } \over 3}} \right)$$

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