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1

### NEET 2016 Phase 2

What is the output Y in the following circuit, when all the three inputs A, B, C are first 0 and then 1 ?

A
0, 1
B
0, 0
C
1, 0
D
1, 1

## Explanation

Applying De Morgan’s law:

Output Y = [(A ⋅ B) ⋅ C]' = A' + B' + C'

When A, B, C are 0 $$\Rightarrow$$ Y = 1

When A, B, C are 1 $$\Rightarrow$$ Y = 0
2

### NEET 2016 Phase 2

The given circuit has two ideal diodes connected as shown in the figure. The current flowing through the resistance R1 will be

A
2.5 A
B
10.0 A
C
1.43 A
D
3.13 A

## Explanation

Current will not flow through D1 as it is reversed biased.

Current will flow through resistor R1, diode D2 and resistor R3

Now current i = 10/(2 + 2) = 2.5 A
3

### NEET 2016 Phase 2

For CE transistor amplifier, the aufio signal voltage across the collector resistance of 2 k$$\Omega$$ is 4 V. If the current amplification factor of the transistor is 100 and the base resistance is 1 k$$\Omega$$, then the input signal voltage is
A
10 mV
B
20 mV
C
30 mV
D
15 mV

## Explanation

Voltage gain, A = $$\beta {{{R_C}} \over {{R_B}}}$$ = $$100 \times {{2000} \over {1000}}$$ = 200

Also, A = $${{{V_0}} \over {{V_i}}}$$

$$\Rightarrow$$ $${V_i} = {{{V_0}} \over A}$$ = $${4 \over {200}}$$ = 20 mA
4

### AIPMT 2015 Cancelled Paper

If in a p-n junction, a square input signal of 10 V is applied, as shown,

then the output across RL will be
A
B
C
D

## Explanation

Here P-N junction diode rectifies half of the ac wave i.e., acts as half wave rectifier.
During + ve half cycle Diode is forward biased output across RL will be

During –ve half cycle Diode is reverse biased output will not obtained.

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NEET

Class 12