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1

AIPMT 2011 Mains

MCQ (Single Correct Answer)
Pure Si at 500 K has equal number of electron (ne) and hole (nh) concentrations of 1.5 $$ \times $$ 1016 m$$-$$3. Doping by indium increases nh to 4.5 $$ \times $$ 1022 m$$-$$3. The doped semiconductor is of
A
p-type having electron concentration ne = 5 $$ \times $$ 109 m$$-$$3
B
n-type with electron concentration ne = 5 $$ \times $$ 1022 m$$-$$3
C
p-type with electron concentration ne = 2.5 $$ \times $$ 1010 m$$-$$3
D
n-type with electron concentration ne = 2.5 $$ \times $$ 1023 m$$-$$3

Explanation

(ni)2 = ne × nh

(1.5 × 1016)2 = ne (4.5 × 1022)

So ne = 5 × 109

Now nh = 4.5 × 1022

$$ \Rightarrow $$ nh $$ >> $$ ne

Hence, semiconductor is p-type

and ne = 5 × 109 m–3
2

AIPMT 2011 Mains

MCQ (Single Correct Answer)
In the following figure, the diodes which are forward biased, are

A
(A), (B) and (D)
B
(C) only
C
(C) and (A)
D
(B) and (D)

Explanation

p-n junction is said to be forward biased when p side is at high potential than n side. It is for circuit (A) and (C).
3

AIPMT 2011 Prelims

MCQ (Single Correct Answer)
In forward biasing of the p-n junction
A
the positive terminal of the battery is connected to p-side and the depletion region becomes thick.
B
the positive terminal of the battery is connected to n-side and the depletion region becomes thin.
C
the positive terminal of the battery is connected to n-side and the depletion region becomes thick.
D
the positive terminal of the battery is connected to p-side and the depletion region becomes thin.

Explanation

In forward biasing, the positive terminal of the battery is connected to p-side and the negative terminal to n-side of p-n junction. The forward bias voltage opposes the potential barrier. Due to it, the depletion region becomes thin.
4

AIPMT 2011 Prelims

MCQ (Single Correct Answer)
Symbolic representation of four logic gates are shown as



Pick out which ones are for AND, NAND and NOT gates, respectively
A
(ii), (iii) and (iv)
B
(iii), (ii) and (i)
C
(iii), (ii) and (iv)
D
(ii), (iv) and (iii)

Explanation

AND, NAND and NOT gates are (ii), (iv) and (iii) respectively.

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