1
MHT CET 2024 9th May Evening Shift
MCQ (Single Correct Answer)
+1
-0

The resultant gate and its Boolean expression in the given circuit is

MHT CET 2024 9th May Evening Shift Physics - Semiconductor Devices and Logic Gates Question 37 English

A
OR, $\mathrm{A+B}$
B
AND, $\mathrm{A - B}$
C
NOR, $\mathrm{A+B}$
D
NAND, $\overline{\mathrm{A}+\mathrm{B}}$
2
MHT CET 2024 9th May Morning Shift
MCQ (Single Correct Answer)
+1
-0

The current amplification factor of a transistor is 50 . The input resistance when used in common emitter mode is $1 \mathrm{k} \Omega$. The peak value for an a.c. input voltage of 0.01 V peak is

A
$100 \mu \mathrm{~A}$
B
0.01 mA
C
0.25 mA
D
$500 \mu \mathrm{~A}$
3
MHT CET 2024 9th May Morning Shift
MCQ (Single Correct Answer)
+1
-0

In the logic circuit diagram, when all the four inputs $\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D}$ are one, the outputs $\mathrm{Y}_1, \mathrm{Y}_2, \mathrm{Y}_3$ are respectively $(1,1,0)$. When all the inputs $\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D}$ are changed to 'zero', the outputs $\mathrm{Y}_1, \mathrm{Y}_2, \mathrm{Y}_3$ respectively change to

MHT CET 2024 9th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 40 English

A
$(0,1,0)$
B
$(0,0,1)$
C
$(1,1,0)$
D
$(1,1,1)$
4
MHT CET 2024 9th May Morning Shift
MCQ (Single Correct Answer)
+1
-0

For the diagram shown, the resistance between points A and B when the ideal diode ' $D$ ' is forward biased is ' $R_1$ ' and that when reverse biased is ' $R_2$ '. The ratio $\frac{R_1}{R_2}$ is

MHT CET 2024 9th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 39 English

A
$\frac{2}{3}$
B
$\frac{2}{5}$
C
$\frac{3}{2}$
D
$\frac{5}{2}$
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