The ripple counter shown in Fig. is made up negative edge triggered $$J$$-$$E$$ flips flops. The signal levels at $$J$$ and $$K$$ inputs of all the flip-flops are maintained at logic $$1$$. Assume that all outputs are cleared just prior to applying the clock signal.

$$(a)$$ Create a table of $${Q_0},{Q_1},{Q_2}$$ and $$A$$ in the format given below for $$10$$ successive
$$\,\,\,\,\,\,\,\,$$ input cycles of the clock $$CLK1.$$
$$(b)$$ Determine the module number of the counter.
$$(c)$$ Modify the circuit of Fig. to create a modulo$$-6$$ counter using the same
$$\,\,\,\,\,\,\,$$ components used in the figure.

For the ring counter shown in Fig. find the steady state sequence if the initial state of the counters is $$1110\,\,(i.e.,\,\,{Q_3},{Q_2},{Q_1},{Q_0} = 1110).$$ Determine the MOD number of the counter.

$$(a)$$ Construct the truth table for the circuit given in Figure $${Q_1},{Q_2}$$ and $${Q_3}$$ are outputs and the clock pulses are the inputs. Unused $$JK$$ inputs are assumed to be at logic $$1.$$ All flip flops are reset at power $$ON$$.
$$(b)$$ Sketch the output waveforms at $${Q_1},{Q_2}$$ and $${Q_3}$$.
$$(c)$$ What function does this circuit perform.