1
GATE CSE 2015 Set 2
Numerical
+1
-0
The minimum number of $$JK$$ flip-flops required to construct a synchronous counter with the count sequence $$\left( {0,0,1,1,2,2,3,3,0,0,...} \right)$$ is ____________.
Your input ____
2
GATE CSE 2015 Set 1
MCQ (Single Correct Answer)
+1
-0.3
Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
A
0, 1, 3, 7, 15, 14, 12, 8, 0
B
0, 1, 3, 5, 7, 9, 11, 13, 15, 0
C
0, 2, 4, 6, 8, 10, 12, 14, 0
D
0, 8, 12, 14, 15, 7, 3, 1, 0
3
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Let $$k = {2^n}.$$ A circuit is built by giving the output of an ݊$$n$$-bit binary counter as input to an $$n$$-to-$${2^n}$$ bit decoder. This circuit is equivalent to a
A
$$k$$-bit binary up counter.
B
$$k$$-bit binary down counter.
C
$$k$$-bit ring counter.
D
$$k$$-bit Johnson counter.
4
GATE CSE 2006
MCQ (Single Correct Answer)
+1
-0.3
You are given a free running clock with a duty cycle of $$50$$% and a digital waveform $$f$$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked $$D$$ flip-flops) will delay the phase of $$f$$ by $${180^0}?$$
A
GATE CSE 2006 Digital Logic - Sequential Circuits Question 12 English Option 1
B
GATE CSE 2006 Digital Logic - Sequential Circuits Question 12 English Option 2
C
GATE CSE 2006 Digital Logic - Sequential Circuits Question 12 English Option 3
D
GATE CSE 2006 Digital Logic - Sequential Circuits Question 12 English Option 4
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