1
GATE CSE 2018
Numerical
+1
-0
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $$D$$ flip-flops. GATE CSE 2018 Digital Logic - Sequential Circuits Question 3 English

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of “in” is _____.

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2
GATE CSE 2016 Set 1
Numerical
+1
-0
We want to design a synchronous counter that counts the sequence $$0-1-0-2-0-3$$ and then repeats. The minimum number of $$J-K$$ flip-flops required to implement this counter is _________.
Your input ____
3
GATE CSE 2015 Set 1
MCQ (Single Correct Answer)
+1
-0.3
Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
A
0, 1, 3, 7, 15, 14, 12, 8, 0
B
0, 1, 3, 5, 7, 9, 11, 13, 15, 0
C
0, 2, 4, 6, 8, 10, 12, 14, 0
D
0, 8, 12, 14, 15, 7, 3, 1, 0
4
GATE CSE 2015 Set 2
Numerical
+1
-0
The minimum number of $$JK$$ flip-flops required to construct a synchronous counter with the count sequence $$\left( {0,0,1,1,2,2,3,3,0,0,...} \right)$$ is ____________.
Your input ____
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