Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.

(ii) The program counter is loaded with the start address of the ISR.

(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

Which one of the following statements is FALSE?

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 $$\mu$$s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 $$\mu$$s to process the keystroke. Let $$T_1$$ denote the fraction of a second spent in polling and processing a keystroke.

In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let $$T_2$$ denote the fraction of a second spent in servicing the interrupt and processing a keystroke.

The ratio $${{{T_1}} \over {{T_2}}}$$ is __________. (Rounded off to one decimal place)