1
GATE CSE 2024 Set 2
MCQ (Single Correct Answer)
+1
-0.33

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

A

2,56,000

B

3,200

C

25,60,000

D

32,000

2
GATE CSE 2024 Set 1
MCQ (Single Correct Answer)
+1
-0.33

Which one of the following statements is FALSE?

A

In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle

B

For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode

C

Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism

D

The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

3
GATE CSE 2023
Numerical
+1
-0.33

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 $$\mu$$s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 $$\mu$$s to process the keystroke. Let $$T_1$$ denote the fraction of a second spent in polling and processing a keystroke.

In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let $$T_2$$ denote the fraction of a second spent in servicing the interrupt and processing a keystroke.

The ratio $${{{T_1}} \over {{T_2}}}$$ is __________. (Rounded off to one decimal place)

Your input ____
4
GATE CSE 2022
MCQ (Single Correct Answer)
+1
-0.33

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

A
DMA based I/O transfer
B
Interrupt driven I/O transfer
C
Polling based I/O transfer
D
Programmed I/O transfer
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