1
GATE CSE 2011
MCQ (Single Correct Answer)
+1
-0.3
A computer handles several interrupt sources of which of the following are relevant for this question.

$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from $$CPU$$ temperature sensor (raises interrupt if $$CPU$$
$$\,\,\,\,\,\,\,\,\,\,\,\,\,\,$$ temperature is too high)
$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from Mouse (raises interrupt if the mouse is moved or a button is
$$\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,$$pressed)
$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from Keyboard (raises interrupt when a key is pressed or released)
$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from Hard Disk (raises interrupt when a disk read is completed)

Which one of these will be handled at the $$HIGHEST$$ priority?

A
Interrupt from Hard Disk
B
Interrupt from Mouse
C
Interrupt from Keyboard
D
Interrupt from $$CPU$$ temperature sensor
2
GATE CSE 2009
MCQ (Single Correct Answer)
+1
-0.3
A $$CPU$$ generally handles an interrupt by executing an interrupt service routine
A
as soon as an interrupt is raised
B
by checking the interrupt register at the end of fetch cycle
C
by checking the interrupt register after finishing the execution of the current instruction
D
by checking the interrupt register at fixed time intervals.
3
GATE CSE 2005
MCQ (Single Correct Answer)
+1
-0.3
Normally user programs are prevented from handling $${\rm I}/O$$ directly by $${\rm I}/O$$ instructions in them. For $$CPUs$$ having explicit $${\rm I}/O$$ instructions, such $${\rm I}/O$$ protection is ensured by having the $${\rm I}/O$$ instructions privileged. In a $$CPU$$ with memory mapped $${\rm I}/O$$, there is no explicit $${\rm I}/O$$ instruction. Which one of the following is true for a $$CPU$$ with memory mapped $${\rm I}/O$$ ?
A
$${\rm I}/O$$ protection is ensured by operating system routine(s)
B
$${\rm I}/O$$ protection is ensured by a hardware trap
C
$${\rm I}/O$$ protection is ensured during system configuration
D
$${\rm I}/O$$ protection is not possible
4
GATE CSE 2004
MCQ (Single Correct Answer)
+1
-0.3
Which one of the following is true for a $$CPU$$ having a single interrupt request line and single interrupt grant line?
A
Neither vectored interrupt nor multiple interrupting devices are possible
B
Vectored interrupts are not possible but multiple interrupting devices are possible
C
Vectored interrupts and multiple interrupting devices are both possible
D
Vectored interrupt is possible but multiple interrupting devices are not possible
GATE CSE Subjects
Software Engineering
Web Technologies
EXAM MAP
Medical
NEET
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
CBSE
Class 12