GATE CSE 2009 | IO Interface Question 10 | Computer Organization

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GATE CSE 2009

MCQ (Single Correct Answer)

-0.3

A $$CPU$$ generally handles an interrupt by executing an interrupt service routine

as soon as an interrupt is raised

by checking the interrupt register at the end of fetch cycle

by checking the interrupt register after finishing the execution of the current instruction

by checking the interrupt register at fixed time intervals.

GATE CSE 2005

MCQ (Single Correct Answer)

-0.3

Normally user programs are prevented from handling $${\rm I}/O$$ directly by $${\rm I}/O$$ instructions in them. For $$CPUs$$ having explicit $${\rm I}/O$$ instructions, such $${\rm I}/O$$ protection is ensured by having the $${\rm I}/O$$ instructions privileged. In a $$CPU$$ with memory mapped $${\rm I}/O$$, there is no explicit $${\rm I}/O$$ instruction. Which one of the following is true for a $$CPU$$ with memory mapped $${\rm I}/O$$ ?

$${\rm I}/O$$ protection is ensured by operating system routine(s)

$${\rm I}/O$$ protection is ensured by a hardware trap

$${\rm I}/O$$ protection is ensured during system configuration

$${\rm I}/O$$ protection is not possible

GATE CSE 2004

MCQ (Single Correct Answer)

-0.3

How many $$8$$-bit characters can be transmitted per second over $$9600$$ baud serial communication link using a parity synchronous mode of transmission with one start bit & Eight data bits, two stop bits, and one parity bit

$$600$$

$$800$$

$$876$$

$$1200$$

GATE CSE 2004

MCQ (Single Correct Answer)

-0.3

Which one of the following is true for a $$CPU$$ having a single interrupt request line and single interrupt grant line?

Neither vectored interrupt nor multiple interrupting devices are possible

Vectored interrupts are not possible but multiple interrupting devices are possible

Vectored interrupts and multiple interrupting devices are both possible

Vectored interrupt is possible but multiple interrupting devices are not possible