1
GATE EE 2023
Numerical
+2
-0.67

Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is ___________.

GATE EE 2023 Digital Electronics - Logic Gates Question 1 English

Your input ____
2
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
$$A,B,C$$ and $$D$$ are input bits, and $$Y$$ is the output bit in the $$XOR$$ gate circuit of the figure below. Which of the following statements about the sum $$S$$ of $$A,B,C,D$$ and $$Y$$ is correct? GATE EE 2007 Digital Electronics - Logic Gates Question 2 English
A
$$S$$ is always either zero or odd
B
$$S$$ is always either zero or even
C
$$S=1$$ only if the sum of $$A,B,C$$ and $$D$$ is even
D
$$S=1$$ only if the sum of $$A,B,C$$ and $$D$$ is odd
3
GATE EE 2005
MCQ (Single Correct Answer)
+2
-0.6
In the figure, as long as $${X_1} = 1$$ and $${X_2} = 1,$$ the output $$Q$$ remains GATE EE 2005 Digital Electronics - Logic Gates Question 5 English
A
at $$1$$
B
at $$0$$
C
at its initial value
D
unstable
4
GATE EE 2004
MCQ (Single Correct Answer)
+2
-0.6
A digital circuit which compares two numbers $${A_3}{A_2}{A_1}{A_0},\,\,{B_3}{B_2}{B_1}{B_0}$$ is shown in Fig. To get output $$Y=0,$$ choose one pair of correct input numbers GATE EE 2004 Digital Electronics - Logic Gates Question 6 English
A
$$1010, 1010$$
B
$$0101,0101$$
C
$$0010, 0010$$
D
$$0010, 1011$$
GATE EE Subjects
EXAM MAP
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12