GATE CSE 2024 Set 1 | Pipelining Question 3 | Computer Organization

GATE CSE 2024 Set 1

MCQ (More than One Correct Answer)

-0.33

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

Forwarding cannot prevent all pipeline stalls

Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

GATE CSE 2023

Numerical

-0.33

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.

The total execution time for executing 100 instructions on this processor is ___________ ns.

Your input ____

GATE CSE 2012

MCQ (Single Correct Answer)

-0.3

as an alternative to register allocation at compile time

for efficient access to function parameters and local variables

to handle certain kinds of hazards

as part of address translation

GATE CSE 2003

MCQ (Single Correct Answer)

-0.3

For a pipelined $$CPU$$ with a single $$ALU$$, consider the following situations
$$1.\,\,\,\,\,$$ The $$j+1$$ instruction uses the result of the $$j$$-$$th$$ instruction as an operand
$$2.\,\,\,\,\,$$ The execution of a conditional jump instruction
$$3.\,\,\,\,\,$$ The $$j$$-$$th$$ and $$j+1$$ instruction require the $$ALU$$ at the same time

Which of the above can cause a hazard?

$$1$$ and $$2$$ only

$$2$$ and $$3$$ only

$$3$$ only

ALL the three

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GATE CSE Subjects

Theory of Computation

Undecidability Finite Automata and Regular Language Push Down Automata and Context Free Language Recursively Enumerable Language and Turing Machine

Operating Systems

Process Concepts and Cpu Scheduling Synchronization and Concurrency Deadlocks Memory Management File System IO and Protection

Algorithms