1
GATE CSE 2024 Set 2
MCQ (More than One Correct Answer)
+1
-0.33

An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-1, source reg-2

Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2

I2: SUB R5, R3, R4

I3: ADD R3, R5, R6

I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

A

There is a RAW dependency on R3 between I1 and I2

B

There is a WAR dependency on R3 between I1 and I3

C

There is a RAW dependency on R3 between I2 and I3

D

There is a WAW dependency on R3 between I3 and I4

2
GATE CSE 2024 Set 1
MCQ (More than One Correct Answer)
+1
-0.33

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

A

In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

B

In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

C

Forwarding cannot prevent all pipeline stalls

D

Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

3
GATE CSE 2023
Numerical
+1
-0.33

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.

The total execution time for executing 100 instructions on this processor is ___________ ns.

Your input ____
4
GATE CSE 2022
Numerical
+1
-0.33

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 90%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ____________.

Your input ____
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