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1

### GATE CSE 2003

For a pipelined $$CPU$$ with a single $$ALU$$, consider the following situations
$$1.\,\,\,\,\,$$ The $$j+1$$ instruction uses the result of the $$j$$-$$th$$ instruction as an operand
$$2.\,\,\,\,\,$$ The execution of a conditional jump instruction
$$3.\,\,\,\,\,$$ The $$j$$-$$th$$ and $$j+1$$ instruction require the $$ALU$$ at the same time

Which of the above can cause a hazard?

A
$$1$$ and $$2$$ only
B
$$2$$ and $$3$$ only
C
$$3$$ only
D
ALL the three
2

### GATE CSE 2000

Comparing the time $$T1$$ taken for a single instruction on a pipelined $$CPU$$ with time $$T2$$ taken on a non-pipelined but identical $$CPU,$$ we can say that
A
$$T1 \le T2$$
B
$$T1 \ge T2$$
C
$$T1 < T2$$
D
$$T1$$ is $$T2$$ plus the time taken for one instruction fetch cycle
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