1
GATE CSE 2023
Numerical
+1
-0.33

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.

The total execution time for executing 100 instructions on this processor is ___________ ns.

Your input ____
2
GATE CSE 2012
MCQ (Single Correct Answer)
+1
-0.3
Register renaming is done in pipelined processors
A
as an alternative to register allocation at compile time
B
for efficient access to function parameters and local variables
C
to handle certain kinds of hazards
D
as part of address translation
3
GATE CSE 2003
MCQ (Single Correct Answer)
+1
-0.3
For a pipelined $$CPU$$ with a single $$ALU$$, consider the following situations
$$1.\,\,\,\,\,$$ The $$j+1$$ instruction uses the result of the $$j$$-$$th$$ instruction as an operand
$$2.\,\,\,\,\,$$ The execution of a conditional jump instruction
$$3.\,\,\,\,\,$$ The $$j$$-$$th$$ and $$j+1$$ instruction require the $$ALU$$ at the same time

Which of the above can cause a hazard?

A
$$1$$ and $$2$$ only
B
$$2$$ and $$3$$ only
C
$$3$$ only
D
ALL the three
4
GATE CSE 2000
MCQ (Single Correct Answer)
+1
-0.3
Comparing the time $$T1$$ taken for a single instruction on a pipelined $$CPU$$ with time $$T2$$ taken on a non-pipelined but identical $$CPU,$$ we can say that
A
$$T1 \le T2$$
B
$$T1 \ge T2$$
C
$$T1 < T2$$
D
$$T1$$ is $$T2$$ plus the time taken for one instruction fetch cycle
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