1
GATE CSE 2012
MCQ (Single Correct Answer)
+2
-0.6
Consider the $$3$$ processes, $$P1,$$ $$P2$$ and $$P3$$ shown in the table.
Process Arrival Time Time Units
Required
P1 0 5
P2 1 7
P3 3 4

The completion order of the $$3$$ processes under the policies $$FCFS$$ and $$RR2$$ (round robin scheduling with $$CPU$$ quantum of $$2$$ time units) are

A
$$FCFS:P1,P2,P3\,\,\,\,RR2:P1,P2,P3$$
B
$$FCFS:P1,P3,P2\,\,\,\,RR2:P1,P3,P2$$
C
$$FCFS:P1,P2,P3\,\,\,\,RR2:P1,P3,P2$$
D
$$FCFS:P1,P3,P2\,\,\,\,RR2:P1,P2,P3$$
2
GATE CSE 2011
MCQ (Single Correct Answer)
+2
-0.6
Consider the following table of arrival time and burst time for three processes $$P0,P1$$ and $$P2$$.
Process Arrival Time Burst Time
P0 0 ms 9 ms
P1 1 ms 4 ms
P2 2 ms 9 ms

The pre-emptive shortest job first scheduling algorithm is used. Scheduling is carried out only a arrival or completion of processes. What is the average waiting time for the three processes?

A
$$5.0$$ $$ms$$
B
$$4.33$$ $$ms$$
C
$$6.33$$ $$ms$$
D
$$7.33$$ $$ms$$
3
GATE CSE 2009
MCQ (Single Correct Answer)
+2
-0.6
In the following process state transition diagram for a uniprocessor system, assume that there are always some processes in the ready state: GATE CSE 2009 Operating Systems - Process Concepts and Cpu Scheduling Question 26 English

Now consider the following statements:
$$1.\,\,\,$$ If a process makes a transition $$D,$$ it would result in another process making transition $$A$$ immediately.
$$2.\,\,\,$$ $$A$$ process $${P_2}$$ in blocked state can make transition $$E$$ while another process $${P_1}$$ is in running state.
$$3.\,\,\,$$ The $$OS$$ uses preemptive scheduling.
$$4.\,\,\,$$ The $$OS$$ uses non-preemptive scheduling. Which of the above statements are TRUE?

A
$$1$$ and $$2$$
B
$$1$$ and $$3$$
C
$$2$$ and $$3$$
D
$$2$$ and $$4$$
4
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
Which of the following is/are true of the auto-increment addressing mode?
$${\rm I}.\,\,\,$$ It is useful in creating self-relocating code
$${\rm II}.\,\,\,$$ If it is included in an Instruction Set Architecture, then an additional $$ALU$$ is required for effective address calculation.
$${\rm III}.\,\,\,$$ The amount of increment depends on the size of the data item accessed
A
$${\rm I}$$ only
B
$${\rm II}$$ only
C
$${\rm III}$$ only
D
$${\rm II}$$ & $${\rm III}$$ only
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