Consider a paging system that uses a 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read in from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal places) is ______.

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the system is $$M$$ units if the corresponding memory page is available in memory, and $$D$$ units if the memory access causes a page fault. It has been experimentally measured that the average time taken for a memory access in the process is $$X$$ units.

Which one of the following is the correct expression for the page fault rate experienced by the process?

Consider a computer system with ten physical page frames. The system is provided with an access sequence $$\left( {{a_1},{a_2},....,{a_{20}},{a_1},{a_2},...,{a_{20}}} \right),$$ where each $${{a_i}}$$ is a distinct virtual page number. The difference in the number of page faults between the last-in-first-out page replacement policy and the optimal page replacement policy is _____________