1
GATE CSE 2006
MCQ (Single Correct Answer)
+2
-0.6
A Computer system supports $$32$$-bit virtual addresses as well as $$32$$-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to get rid of the virtual memory entirely. Which one of the following is true?
A
Efficient implementation of multi-user support is no longer possible.
B
The processor cache organization can be made more efficient now.
C
Hardware support for memory management is no longer needed.
D
$$CPU$$ scheduling can be made more efficient now.
2
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
Consider a System with a two-level paging scheme in which a regular memory access takes $$150$$ nanoseconds, and servicing a page fault takes $$8$$ milliseconds. An average instruction takes $$100$$ nanoseconds of $$CPU$$ time, and two memory accesses. The $$TLB$$ hit ratio is $$90$$% and the page fault rate is one in every $$10,000$$ instructions. What is the effective average instruction execution time?
A
$$645$$ nanoseconds
B
$$1050$$ nanoseconds
C
$$1215$$ nanoseconds
D
$$1230$$ nanoseconds
3
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
Which of the following is NOT an advantage of using shared, dynamically linked libraries as opposed to using statically linked libraries?
A
Smaller sizes of executable files
B
Lesser overall page fault rate in the system
C
Faster program startup
D
Existing programs need not be re-linked to take advantage of newer versions of libraries.
4
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $$10$$ most significant bits of the virtual address are used as index into the first level page table while the next $$10$$ bits are used as index into the second level page table. The $$12$$ least significant bits of the virtual address are used as offset within thepage. Assume that the page table entries in both levels of page tables are $$4$$ bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of $$96$$%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of $$90$$%. Main memory access time is $$10$$ ns, cache access time is $$1$$ ns, and TLB access time is also $$1$$ ns.

Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest $$0.5$$ ns)

A
$$1.5$$ ns
B
$$2$$ ns
C
$$3$$ ns
D
$$4$$ ns
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