GATE CSE 2022 | Memory Management Question 7 | Operating Systems

GATE CSE 2022

MCQ (Single Correct Answer)

-0.67

Which one of the following statements is FALSE?

The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address.

If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory.

The memory access time using a given inverted page table is always same for all incoming virtual addresses.

In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same.

GATE CSE 2022

Numerical

-0

Consider a demand paging system with four page frames (initially empty) and LRU page replacement policy. For the following page reference string

7, 2, 7, 3, 2, 5, 3, 4, 6, 7, 7, 1, 5, 6, 1

the page fault rate, defined as the ratio of number of page faults to the number of memory accesses (rounded off to one decimal place) is _____________.

Your input ____

GATE CSE 2021 Set 2

Numerical

-0

Consider a three-level page table to translate a 39-bit virtual address to a physical address as shown below.

GATE CSE 2021 Set 2 Operating Systems - Memory Management Question 9 English

The page size is 4 KB (1 KB = 2¹⁰ bytes) and page table entry size at every level is 8 bytes. A process P is currently using 2 GB (1 GB = 2³⁰ bytes) virtual memory which is mapped to 2 GB of physical memory. The minimum amount of memory required for the page table of P across all levels is _______ KB.

Your input ____

GATE CSE 2020

Numerical

-0

Consider a paging system that uses a 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read in from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal places) is ______.

Your input ____