Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the system is $$M$$ units if the corresponding memory page is available in memory, and $$D$$ units if the memory access causes a page fault. It has been experimentally measured that the average time taken for a memory access in the process is $$X$$ units.

Which one of the following is the correct expression for the page fault rate experienced by the process?

Consider a computer system with $$40$$-bit virtual addressing and page size of sixteen kilobytes. If the computer system has a one-level page table per process and each page table entry requires $$48$$ bits, then the size of the per-process page table ____________ is megabytes.

Consider a computer system with ten physical page frames. The system is provided with an access sequence $$\left( {{a_1},{a_2},....,{a_{20}},{a_1},{a_2},...,{a_{20}}} \right),$$ where each $${{a_i}}$$ is a distinct virtual page number. The difference in the number of page faults between the last-in-first-out page replacement policy and the optimal page replacement policy is _____________