State whether the following statements are TRUE or FALSE with reason. Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.

Match the pairs in the following Question.
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,List:\,{\rm I} \cr & \left( A \right)\,\,Criotical\,\,region \cr & \left( B \right)\,\,Wait/Signal \cr & \left( C \right)\,\,Working\,\,set \cr & \left( D \right)\,\,Deadlock \cr & \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,List:\,{\rm I}{\rm I} \cr & \left( p \right)\,\,Hoare's\,\,monitor \cr & \left( q \right)\,\,Mutual\,\,exclusion \cr & \left( r \right)\,\,\Pr inciple\,\,of\,\,locality \cr & \left( s \right)\,\,Circular\,\,Wait \cr} $$

Under paged memory management scheme simple lock and key memory protection arrangement may still be required if the $$........$$ processors do not have address mapping hardware.

In a two -level virtual memory, the memory access time for main memory, $${t_M} = {10^{ - 8}}\sec $$ and the memory access time for the secondary memory, tag $$ = {10^{ - 3}}.$$ What must be the hit ratio, $$H$$ such that the access efficiency is within $$80$$ percent of its maximum value?