1
GATE ECE 2017 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The Nyquist plot of the transfer function $$G(s) = {k \over {\left( {{s^2} + 2s + 2} \right)\left( {s + 2} \right)}}$$ does not encircle the point (-1+j0) for K = 10 but does encircle the point (-1+j0) for K = 100. Then the closed loop system (having unity gain feedback) is
A
stable for K = 10 and stable for K = 100
B
stable for K = 10 and unstable for K = 100
C
unstable for K = 10 and stable for K =100
D
unstable for K = 10 and unstable for K = 100
2
GATE ECE 2017 Set 1
MCQ (Single Correct Answer)
+1
-0.3
Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?
A
GATE ECE 2017 Set 1 Control Systems - Compensators Question 17 English Option 1
B
GATE ECE 2017 Set 1 Control Systems - Compensators Question 17 English Option 2
C
GATE ECE 2017 Set 1 Control Systems - Compensators Question 17 English Option 3
D
GATE ECE 2017 Set 1 Control Systems - Compensators Question 17 English Option 4
3
GATE ECE 2017 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Which one of the following gives the simplified sum of products expression for the Boolean function $$F = {m_0} + {m_2} + {m_3} + {m_5},$$ where $$F = {m_0} + {m_2} + {m_3} + {m_5},$$ are minterms corresponding to the inputs A, B and C with A as the MSB and C as the LSB?
A
$$\overline A B + \,\overline A \,\overline B \,\overline C + \,A\overline B \,C$$
B
$$\overline A \,\overline C + \overline A B + A\overline B C$$
C
$$\overline A \,\overline C + A\,\overline B + A\overline B C$$
D
$$\overline A \,BC + \overline A \,\overline C + A\,\overline B C$$
4
GATE ECE 2017 Set 1
Numerical
+1
-0
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________. GATE ECE 2017 Set 1 Digital Circuits - Sequential Circuits Question 48 English 1 GATE ECE 2017 Set 1 Digital Circuits - Sequential Circuits Question 48 English 2
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