1
GATE ECE 2017 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Which one of the following gives the simplified sum of products expression for the Boolean function $$F = {m_0} + {m_2} + {m_3} + {m_5},$$ where $$F = {m_0} + {m_2} + {m_3} + {m_5},$$ are minterms corresponding to the inputs A, B and C with A as the MSB and C as the LSB?
A
$$\overline A B + \,\overline A \,\overline B \,\overline C + \,A\overline B \,C$$
B
$$\overline A \,\overline C + \overline A B + A\overline B C$$
C
$$\overline A \,\overline C + A\,\overline B + A\overline B C$$
D
$$\overline A \,BC + \overline A \,\overline C + A\,\overline B C$$
2
GATE ECE 2017 Set 1
Numerical
+1
-0
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________. GATE ECE 2017 Set 1 Digital Circuits - Sequential Circuits Question 48 English 1 GATE ECE 2017 Set 1 Digital Circuits - Sequential Circuits Question 48 English 2
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3
GATE ECE 2017 Set 1
MCQ (Single Correct Answer)
+1
-0.3
In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = "0‟. If the input condition is changed simultaneously to P = Q = "1", the outputs X and Y are GATE ECE 2017 Set 1 Digital Circuits - Sequential Circuits Question 47 English
A
X = '1', Y = '1'
B
either X = '1', Y = '0' or X = '0', Y = '1'
C
either X = '1', Y = '1' or X = '0', Y = '0'
D
X = '0', Y = '0'
4
GATE ECE 2017 Set 1
Numerical
+2
-0
A 4-bit shift register circuit configured for right-shift operation is $${D_{in}}\, \to \,A,\,A\, \to B,\,B \to C,\,C \to D,$$ is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is GATE ECE 2017 Set 1 Digital Circuits - Sequential Circuits Question 23 English
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